True Charge Domain Time Delay Integration
Back Side Illuminated (BSI) pixels
High Sensitivity with QE of 63.9% (266 nm) and 93.4% (440 nm)
High Speed: up to 1 MHz
HDR Read Out
On-chip Binning
Resolution
8.2K
Nr of Active Pixels
P1: 8208 pixels x 256 stages P2: 8208 pixels x 32 stages
Optical Format
41.04 mm
Pixel Size
5 μm x 5 μm
Full Well Capacity
16.8 ke⁻ (P1,10 bit,single band) 17.8 ke⁻ (P1,12 bit,single band)
Temporal Noise
12.1 e⁻ (P1,10 bit,single band) 7.4 e⁻ (P1,12 bit,single band)
Dynamic Range
62.8 dB (P1,10 bit,single band) 67.6 dB (P1,12 bit,single band)
Max Line Rate
1M Hz (10 bit) 500k Hz (12 bit)
Peak QE
63.9% (266 nm) 93.4% (440 nm)
Shutter Type
Time Delay Integration
Photosensive Area
P1: 41.04 mm x 1.28 mm P2: 41.04 mm x 0.16 mm
Dark Current
1 ke⁻/pixel/s (P1 10/12 bit,single band,15 ℃)
Max. SNR
42.3 dB (10 bit)
ADC
10/12 bit
Output Format
72 ch Sub-LVDS (10 bit)
Channel Multiplexing
72/54/48/36/24/18/12/6 (10 bit)
Max. Data Rate
86.4 Gbps (10 bit)
Chroma
Mono
Power Consumption
≤ 4.1 W (P1,10 bit,1 MHz line rate) ≤ 3.2 W (P1,12 bit,500 kHz line rate)
Supply Voltage
3.3 V (analog) 1.65 V (ADC) 1.6 V (digital)
Package
μPGA 231 pins (56.90 mm x 19.00 mm)
Availability
Engineering Samples (ES)
