True Charge Domain Time Delay Integration
Back Side Illuminated (BSI) pixels
High Sensitivity with QE of 70.7% (266 nm)(UV Version) and up to 92.4 % (440 nm)(VIS version)
High Speed: up to 500 kHz
HDR Read Out
On-chip Binning
Resolution
16.4K
Nr of Active Pixels
P1: 16416 pixels x 256 stages P2: 16416 pixels x 32 stages
Optical Format
82.02 mm
Pixel Size
5 μm x 5 μm
Full Well Capacity
16.3 ke⁻ (P1,10 bit,single band) 15.2 ke⁻ (P1,12 bit,single band)
Temporal Noise
7.5 e⁻ (P1,12 bit,single band) 15.3 e⁻ (P1,10 bit,single band)
Dynamic Range
60.5 dB (P1,10 bit,single band) 66.1 dB (P1,12 bit,single band)
Max Line Rate
500 kHz
Peak QE
UV version: 70.7% (266 nm), 87.8% (420 nm) VIS version: 92.4% (436 nm), 87.0% (590 nm)
Shutter Type
Time Delay Integration
Photosensive Area
P1: 82.08 mm × 1.28 mm P2: 82.08 mm × 0.16 mm
Dark Current
0.97 ke‾/pix/sec (15℃)
Max. SNR
41.7 dB
ADC
12 bit
Output Format
108 ch Sub-LVDS
Channel Multiplexing
108/96/72/48/36/24/12
Max. Data Rate
103.68 Gbps
Chroma
Mono
Power Consumption
≤ 6.3 W (P1,10 bit,500 kHz line rate) ≤ 6.6 W (P1,12 bit,500 kHz line rate)
Supply Voltage
3.3 V (analog) 1.65 V (ADC) 1.6 V (digital)
Package
μPGA 415 pins (98.08 mm x 19.00 mm)
Availability
Engineering Samples (ES)
